The rapid increase in processor speed has necessitated a commensurate increase in memory access speed of off-chip caches or memory to prevent memory accesses from becoming a bottleneck. Traditionally, access to off-chip memory devices has been in accordance with a synchronous protocol. Synchronous protocols, in which off-chip accesses have a guaranteed bounded recurring latency relationship, have been easy to implement and are well defined. Synchronous protocols generally have been implemented by a clock that distributes a clock signal to an on-chip controller and to the off-chip caches or memory. Accesses are initialized and terminated only at transitions in value of the clock signal.
However, interfaces for which synchronous protocols are used are limited by a physical delay between communicating devices. System design requires a uniform clock among the various devices, mandating that clock wires be routed across the interface, increasing complexity of design. Due to these limitations, source-synchronous protocols are increasingly the interface of choice for higher speed off-chip interfaces.
In a source-synchronous interface, a source provides data and/or a command and a timing reference that accompanies the data and/or command. The source expects the recipient to capture the data and/or command based on the timing reference. The timing reference allows the recipient to receive the data and/or command despite lack of any timing relationship between the source and the recipient, creating an asynchronous boundary at the recipient. Interfaces for which source-synchronous protocols are used allow devices in distinct timing domains to exchange data despite a lack of a common clock. For example, an on-chip controller in a first timing domain can exchange data with an off-chip cache or memory in a second timing domain. Source-synchronous data transfers between devices in different timing domains can be complicated by latency, complexity, and a lack of repeatability. “Repeatability,” in this context, is defined as a lack of deviation in latency between an access and a subsequent access.
Traditionally, two main avenues have been followed when implementing source-synchronous interfaces. First, the read latency due to the asynchronous nature of the interface has been allowed to vary from access to access. This variance hampers debugging of a processor where cycle reproducibility is required. The difficulty of debugging is further compounded when two processors with minor manufacturing differences are not comparable on a cycle-to-cycle basis. The second approach for implementing a source-synchronous system addresses the reproducibility issue by creating a software interface that allows the operating system to set the latency for all accesses. The software interface, while maintaining reproducibility, requires the system designer to manually calculate the latency of an interface including all wiring delays. The novel invention described herein provides the reproducibility of the software interface, while hiding wiring and other latency details from the system designer. Since the ability to be cycle-reproducible is critical in the debugging of a system in a lab, and the time-consuming task of manually calculating interface latency is hidden from a system designer, the invention described herein can have a positive impact on the time-to-market period of a new system, thus improving overall revenue.
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